1. Field of the Invention
The present invention relates to an image processing apparatus, an image forming apparatus and an image processing method.
2. Description of the Related Art
Devices such as scanners and video cameras have become widely available as input devices in recent years. On the other hand, various color printers using inkjet, dye-sublimation and electrophotographic methods have become widespread as output devices. These color input and output devices have their own color spaces. For example, in a case where a color image obtained by a certain scanner is printed as is upon being transferred to a separate color printer, the colors in the printed color image will differ from the colors in the original color image read by the scanner owing to the difference in the color spaces.
In order to solve this problem of color reproducibility of color images between devices, processing (referred to as “color-space conversion processing” below) for converting the color space of the input device to the color space of the output device is required. In order to improve color reproducibility between input and output devices, there are instances where the input and output devices are equipped with an image processing circuit having a color-space conversion function.
For example, the specification of Japanese Patent Application Laid-Open No. 2004-274131 proposes a color conversion apparatus in which an image processing circuit having a color-space conversion function is provided with a cache mechanism, and a three-dimensional look-up table (3D-LUT) that stores reference values necessary for color-space conversion is stored in an external memory such as a DRAM.
According to Japanese Patent Application Laid-Open No. 2004-274131, color space used in an interpolation operation is modeled as a unit cube, a small-capacity internal SRAM is assigned to each vertex of the unit cube, and the internal SRAM is used as a cache memory.
With an ordinary direct-mapping-type cache mechanism, the storage destination of the cache memory is decided by the lower-order bits of a color-space address. Consequently, there are instances where storage destinations contend between successive items of image data and the cache mechanism does not function effectively. In other words, when items of image data for which the lower-order bits of the addresses are the same but the higher-order bits are different continue to be input alternatingly, the cache memory is overwritten alternatingly and mishits occur.
When a direct-mapping cache mechanism experiences a mishit, only data necessary when interpolation is executed is read out of the external memory (DRAM) having the 3D-LUT, the cache memory is updated and the interpolation is executed. By providing the image processing circuit for color-space conversion with the cache mechanism, it is possible to reduce the capacity of the internal SRAM.
However, in a case where image processing is executed by the image processing circuit equipped with the cache mechanism, a problem which arises is a decline in processing capability when the cache mechanism experiences a mishit. The image processing circuit ceases operating and image processing can no longer be executed until the mishit in the cache mechanism is discriminated, the desired data is read out of the external memory such as the DRAM and the cache memory is updated.
Waiting time for this updating of data is referred to as “refill latency”. The longer refill latency is, the more processing capability declines when a mishit occurs in the cache mechanism. A common solution that can be mentioned is to suppress the decline in processing capability by increasing the capacity of the cache memory and reducing the frequency of mishits.
However, the frequency of mishits depends upon statistical bias of the input image data to the image processing circuit and merely increasing the capacity of the cache memory is not a satisfactory solution. Further, a solution that calls for a great increase in the capacity of the cache memory runs counter to a reduction in LSI manufacturing cost, which was the original reason for providing the cache memory.
Besides considering techniques for reducing the frequency of mishits in the cache, minimization of refill latency when mishit has occurred and a reduction in the degree of the decline in mishit processing capability are sought.
Constructing an image processing system having little refill latency leads to construction of a stable image processing system that is independent of statistical bias of input image data. However, such a method of reducing refill latency is not disclosed in Japanese Patent Application Laid-Open No. 2004-274131.
Further, in an image processing apparatus such as a printer, there has been a tendency in recent years to raise the resolution of image processing greatly in order to improve image quality. A solution to raising the resolution of image processing is to raise the operating frequency of the LSI chip. However, in the case of consumer-product-oriented LSI chips, various problems such as power consumption arise, and there are also cases in which the solution that entails raising LSI operating frequency cannot be reflected. In such cases, consideration has been given to improving processing capability per unit operating frequency by placing image processing circuits in parallel and processing a plurality of pixels in parallel.
However, with image processing in which a 3D-LUT is referred to randomly per series of pixels to be processed, as in a color-space conversion, implementing the parallel processing of a plurality of pixels is difficult as long as the same 3D-LUT is not provided in duplicate for every image processing circuit placed in parallel.